A study of substrate noise in mixed-signal integrated circuits

Abstract

Integrating analog and radio-frequency (RF) circuits with digital blocks on a C M O S system-on-a-chip (SoC) has drawn a lot of attention, recently. One major obstacle at this high level of integration is the substrate noise, which results in undesired interaction between these circuits through the common substrate. Analog circuits are the main victims of such interactions; consequently, understanding the behaviour of substrate noise and performance degradations it causes, is indispensable for analog designers. This work addresses three aspects of substrate noise. First, substrate noise is characterized in the time and frequency domains to identify major parameters that control substrate noise generation, propagation, and reception. Effects of many parameters on the amount of noise generation and coupling are also studied. Second, this thesis investigates the noise impact on analog circuits from a circuit-level point of view by introducing a new small-signal model of the M O S device, which accounts for the substrate noise effects. While most works have focused on system-level or signallevel analysis, study of the noise from a circuit-level point of view is more beneficial for analog designers because it gives them more insight on how to improve the substrate noise rejection capability of their designs. Finally, noise reduction techniques are revisited in this work. The use of passive guardrings is reviewed in detail and the effects of many design parameters on the amount of noise attenuation provided by these structures are studied. The behaviour of guard-rings in different substrates are also discussed.