Substitution Box Optimization

Abstract

The basic principle of encryption is to transform plain data into unintelligible data via a series of steps referred to as an encryption algorithm. The input to this algorithm is called plaintext, and its output encoded version is called as cipher text. Even though there are various algorithms, Advanced Encryption Standard (AES) is adopted due to the availability of optimized hardware components for efficient implementation. The S-Box is one of the critical operations in AES algorithm and it consists of two sub-modules, namely the multiplicative inversion sub-module in GF(2^8) and the Affine transformation sub-module Each input to the S-Box is a 1-byte of intermediate data, x, and the S-Box will generate 1-byte of output S(x). There are variety of methods can used to implement AES S box. Through this project our aim is to optimize the S box for minimal access time. We are planning to implement an optimized implementation of the S-box in the Verilog HDL. By developing the Verilog code for substitution box by using different methods, compare them and implement the same in hardware using FPGA.