Design of a Specific Instructions Set Processor for AES Algorithm

Abstract

ABSTRACT In this paper, a new architecture for Advanced Encryption Standard (AES) Algorithm based on Application Specific Instruction set Processors (ASIP) design technique is proposed. The basic configuration is developed in order to reduce the execution clock pulses for the main specific instructions. According to the improvement of the first register configuration, two ASIPs are designed for AES algorithm. The second ASIP is 89% faster and have 22% less gates than the first proposed design. Keywords ASIP, AES algorithm, RTL, crypto Processor 1. INTRODUCTION Today, cryptography has been widely used to achieve information security. Cryptography is a fundamental part of communication and many other digital applications. Data Encryption Standard Algorithm (DES) was the standard encryption algorithm from 1974 till 1999. In 2000, the National Institute of Standards and Technology (NIST) selected the Rijndael algorithm as the new Advanced Encryption Standard (AES) algorithm [1]. AES is a symmetric algorithm that provides an excellent combination of security, performance, efficiency and flexibility [2, 3]. The AES algorithm can also be efficiently implemented on hardware and software platforms [3]. Software implementations of encryption algorithms have the lower cost and higher flexibility in comparison with the hardware implementations. However, the speed of software execution is much lower than the hardware implementation. The AES hardware implementations provide the highest speed for the real-time applications [3]. Many researches have been recently done on different hardware implementations, using ASIC [4, 5] and FPGA technologies [3, 6]. An Application Specific Instruction set Processor (ASIP) is a technique of designing a system on chip with the aim of achieving speed and programmability. The instruction set of an ASIP is selected to operate a specific application. This specialization of the Processor provides a tradeoff among the flexibility, performance and speed of a hardware implementation on FPGA and ASIC platforms. ASIPs have the advantage of both programmability and efficiency at the same time [7]. The implementation and design of Application Specific set Instruction Processor (ASIP) are relatively less explored in the literature [8]. In this work, an ASIP-based design for AES algorithm is proposed. The main register configuration is according to the architecture presented by M. Mano. Then, it is gradually modified to increase speed and flexibility. The rest of the paper is organized as follows. The AES algorithm is introduced in Section 2, the proposed ASIP designs for AES algorithm is presented in Section 3. The conclusion is in section 4.