Submicron MOS process with 10:1 optical-projection printing and anisotropic dry etching

Abstract

Results of an n-MOS process with minimum feature sizes in the submicron range are reported. Lithography is realised by 10:1 optical printing with step-and repeat exposure. Minimum linewidths of 0.7μm have been achieved using a high numerical aperture projection optics with 0.42NA. In order to obtain high fidelity in pattern transfer, anisotropic dry-etching techniques have been used for all levels. Results are given for the patterning of the TaSi2In+-poly stack, and an aluminium etching process with BCl3/Cl2 is discussed in detail. Reducing the gate oxide thickness to 12.5nm, transistors have been optimised forminimum short-channel effects down to 0.5μm channel length. The limiting gate and drain voltages for the submicron devices have been determined. For a supply voltage of 3 V, negligible long-term transistor degradation is extrapolated. The effect of scaling of the lateral dimension on the field isolation and contact hole resistance is investigated. Exploratory dynamic RAM cell arrays with a cell area 37 μm2 and a cell capacitanceof 36 fF have been fabricated and characterised.