Submicrometer Ultralow-Power TFT With 1.8 nm NAOS $ \hbox{SiO}_{2}/\hbox{20} \ \hbox{nm}$ CVD $\hbox{SiO}_{2}$ Gate Stack Structure

Abstract

We have fabricated submicrometer ultralow-power thin-film transistors (TFTs) with stack gate dielectric structure formed by the nitric acid oxidation of Si (NAOS) method. A 1.8 nm NAOS SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer effectively blocks the leakage current, and consequently, the thickness of a gate oxide layer deposited on the NAOS SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer can be made as thin as 20 nm. Because of the thin gate oxide layer, submicrometer TFTs with gate length in the range of 0.6-0.9 μm can be fabricated. The operation voltage of the TFTs can be set as low as 1.5 V because of the low threshold voltages (i.e., -0.6 V for P-ch TFT and 0.6 V for N-ch TFT). The drain current versus source-drain voltage curves possess an ideal feature with sufficiently high saturation currents even at 1.5 V operation voltage. The drain current versus gate voltage curves show a sharp current increase, and the subthreshold swing value is ~80 mV/dec for both P-ch and N-ch TFTs. The on/off ratio is ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> for both P-ch and N-ch TFTs, and the channel mobility is ~100 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for P-ch TFT and ~200 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for N-ch TFT.