Abstract
The combination of sub-melt laser annealing plus low-temperature rapid thermal annealing (the V/sup 2/LTP Process) has been investigated for the formation of shallow doped regions with minimal thermal diffusion and without melting. In particular, the process can be used to form ultra-shallow, low sheet resistance junctions or deeper regions where thermal diffusion after implant is undesired. In this two-step process an implanted wafer is first laser annealed using a laser energy density that achieves a high wafer temperature (1100-1300/spl deg/C) but does not melt the silicon (sub-melt). This step achieves dopant activation to the desired level. Finally, the wafer is annealed with a low-temperature (650-850/spl deg/C) rapid thermal anneal. This process repairs crystalline damage from the implant so that devices have good mobilities and low leakage currents. SIMS and sheet resistance data have been measured for a wafer implanted with 1 keV B/sup +/ ions to a dose of 9/spl times/10/sup 14/ cm/sup -2/, then laser annealed below the melting threshold with 100 laser pulses, and finally rapid annealed at 700/spl deg/C for 20 sec. The SIMS profiles clearly show that no measurable diffusion has occurred during the V/sup 2/LTP process, and yet a sheet resistance of 360 /spl Omega/sq. was produced.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call