Subhalf-micrometer buried-channel PFET design considerations

Abstract

Design considerations for sub-half-micrometer buried-channel PFETs are discussed for 3.3-V technology applications. The device technology uses scaled gat-oxide thickness (14 nm), salicided gate electrode and junctions, and high-temperature glass passivation. Conventional designs using a uniform n-well profile (UNW) require, on scaling, increased doping level to control short-channel effects such as FET threshold and punchthrough voltage reduction. This results in increased junction capacitance, wider FET threshold-voltage tolerance, and decreased low-field hole mobility. Reduction of these effects is accomplished with a nonuniform n-well profile, referred to as a tailored n-well (TNW). Tailored n-well profiles have been achieved with deep phosphorus implants (DPI). Modeled profiles compare well with experimental results from devices fabricated with DPI in the range of 150 to 200 keV. The TNW devices equal of exceed the short-channel characteristics of the UNW devices, with junction capacitance reduced by 40%. Improvements in linear transconductance and threshold-voltage have also been achieved. Additional improvements in PFET performance are possible by reduction of parasitic overlap capacitance and device series resistance. >