An elevated source/drain-on-insulator structure to maximize the intrinsic performance of extremely scaled MOSFETs

Abstract

In this paper, a source/drain structure separated from the silicon substrate by oxide isolation is fabricated and studied. The source/drain diffusion regions are connected to the shallow source/drain extension through a smaller opening defined by a double spacer process. Experimental results indicate that the source/drain on insulator significantly reduces the parasitic capacitance. Further optimization by simulation indicates a reduction of series resistance and band-to-band drain leakage at off-state can be achieved in extremely scaled devices. Compared with the conventional planner source/drain structure, the reduction of parasitic capacitance and series resistance can be as much as 80% and 30% respectively.