Sub-50-nm physical gate length CMOS technology and beyond using steep halo

Abstract

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 /spl mu/A//spl mu/m for an off current of less than 10 nA//spl mu/m at 1.2 V with T/sub ox//sup inv/=2.5 nm. For an off current less than 300 nA//spl mu/m, 33-nm pMOSFETs have a high drive current of 400 uA//spl mu/m. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 /spl mu/A//spl mu/m for an off current of less than 300 /spl mu/A//spl mu/m at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions.