Abstract

Abstract SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.

Highlights

  • The Internet of Things (IoT) is a very rapidly growing market, with 20 billion of connected devices expected by 2020

  • We detail process definition and optimization leading to a Process of Reference (PoR), which we evaluate in terms of Critical Dimension (CD) uniformity and reproducibility

  • The Focused Ion Beam (FIB) NVision 40 from Zeiss Microscopy, and the Energy-Filtered Transmission Electron Microscopy (EFTEM) Titan 80–300 from FEI equipped with the “Gatan Tridiem 863” energy filter, are both installed at HZDR

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Summary

Introduction

The Internet of Things (IoT) is a very rapidly growing market, with 20 billion of connected devices expected by 2020. A critical constraint for those devices is to offer low power consumption [1]. In this context, single-electron-transistors (SETs), consisting of a quantum dot lying between two tunneling junctions to neighbor drain and source Si re­ gions, arise growing interest [2]. Vertical nanopillar based SETs in gate-all-around configuration, where the quantum dot is a Si nanodot embedded in a SiO2 layer, are promising candidates to offer both low power consumption and an enhanced gate control [3,4]. NPs of such dimensions have already been patterned, but either the processes and materials do not meet the CMOS industry standards, or the NPs are single-layer structures [7,8]. We detail process definition and optimization leading to a Process of Reference (PoR), which we evaluate in terms of CD uniformity and reproducibility

Process equipments and materials
Structural characterization
CD measurement
Patterning stack definition
Resist thickness and coating delay
Process uniformity and reproducibility
Conclusion
Gharbi
Full Text
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