Sub-1 V embedded SRAM with bit-error immune dual-boosted cell technique

Abstract

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 µm 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 µW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM.