Studying Trapped Tunneling-Electron Migration Due to Program and Erase Cycles in NAND Flash

Abstract

With the technology scaling, cell-to-cell interference becomes larger in NAND flash memories. This makes it challenging to obtain narrow threshold voltage ( $\text{V}_{\mathrm{ th}})$ distribution in two times nanometer floating gate technologies. Moreover, $\text{V}_{\mathrm{ th}}$ distribution is further degraded after experiencing program and erase (P/E) cycles, impeding reliable operations. In this letter, we find that $\text{V}_{\mathrm{ th}}$ values of programmed cells transiently increases after programming execution, leading to different $\text{V}_{\mathrm{ th}}$ values between verify and read operations. This effect becomes worse by P/E cycles, degrading the $\text{V}_{\mathrm{ th}}$ distribution of the programmed cells after P/E cycles. We consider that such a phenomenon occurs, since the electric field across tunneling oxide makes trapped tunneling-electrons migrate to other trap sites inside the oxide, namely, trapped tunneling-electron migration (TTEM). Our experiments show that the effect of TTEM can be significantly reduced by applying negative pulse between programming pulse and verifying. This informs that using such a technique, we are able to improve the reliability of NAND flash memories after P/E cycles.