Nimble Mapping SSD: Leaning State Mapping Strategy to Increase Reliability of 3D TLC Charge-Trap NAND Flash Memory

Abstract

With the adoption of vertical stacked structure and charge-trap cell design, 3D NAND flash memory reduces the cost-per-bit and becomes the mainstream in the storage market. Since every operation can cause the damage to NAND flash memory and increase the error bits, each cell in NAND flash memory can endure only limited write and erase operations. While the bit errors are highly related to the data pattern, conventional works such as data randomization distribute the threshold voltage states uniformly to prevent the worse-case data pattern. However, data randomization may miss the opportunity to improve the SSD’s lifetime because the distribution of threshold voltage states is uniform whatever the access behavior. In 3D charge trap NAND flash, as the lower states would incur more right shifting than a cell with higher states, the access behavior may influence the bit errors. In this paper, we propose a error mitigation scheme to improve reliability of NAND flash-memory storage devices by utilizing the characteristic of 3D charge trap NAND flash memory to encode the written data asymmetrically. Compared with the related work, our proposed Nimble Mapping SSD (NMS) could improve the reliability with less memory overhead. For the retention error, NMS has similar encoding effect, and the experiment results showed that the BER is averagely 1.2% lower than the related work. Furthermore, NMS could reduce the BER of program variation by 17.1% on average.