Abstract
Recently, mutli-channel aggregation has been considered, e.q. in IEEE 802.20 (MBTDD 625 k-MC mode), to achieve higher throughput on legacy wireless systems. To realize such a system, a multi-channel digital down converter (DDC) is needed for the receiver. In a conventional scheme, parallel DDCs are used to implement the mutli-channel DDC. However, such architecture results in a high computational cost. In this paper, a new circuit architecture for multi-channel DDC based on a polyphase filter and DFT filter bank is studied. By using the proposed architecture, the number of multipliers (the circuit size) can be reduced significantly compared with the conventional mutli-channel DDC while maintaining power consumption.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
