An efficient structure for run-time configuration of synthesis and channelizer filter banks

Abstract

The ability to change frequency and adjust bandwidth in a digital receiver is a fundamental property of Software Defined Radios (SDRs). FPGAs are ideal candidates for handling the high computational load required for high sampling rates. In this paper an efficient method for either combining or channelizing varying bandwidth signals within a single filter structure in hardware is presented. The two methods are a synthesis polyphase filter bank (PFB) and a channelizer PFB. The synthesis PFB is implemented as an M-point inverse Discrete Fourier Transform (DFT) followed by an M-path polyphase filter bank, which is modified to oversample the input channel, limiting aliasing between channels. The channelizer PFB is implemented as the reverse process: a D-path PFB followed by a D-point inverse DFT. The channelizer structure is similarly modified to produce output channels that are 2x oversampled. This structure can accommodate a large number signals with large variations in bandwidth, and allows them to be combined or channelized efficiently.