Study on Interface Engineering of TiN/SiO2 Layers to Reduce the Parasitic Capacitance in CMOS Circuits

Abstract

Recent developments in CMOS (Complementary Metal-Oxide-Semiconductor) technology have heightened the need for high-quality interface between mold and metal line, in order to decrease the RC delay in CMOS circuit. This technical trend indicates that the understanding of the interface reaction between the silicon dioxide (SiO2) and the titanium nitride (TiN) is emerging as an important issue in the thin film deposition process. However, only few researchers have focused on the interface researches to investigate the formation of parasitic capacitance and its material properties of TiN/SiO2 layer. In this work, we report the formation mechanism of Titanium dioxide (TiO2) on SiO2 surface during the TiN deposition process based on a Plasma Enhanced Chemical Vapor Deposition (PECVD) and Titanium tetrachloride (TiCl4) gas reactions. This research has explored the effects of the partial pressure of TiCl4 gas in the initial step of TiN deposition on the formation of the intermetallic compound of TiN/SiO2 interface layer. The results of atomic composition and the position of valance band of the composite material analyzed by X-ray photoelectron spectroscopy (XPS) reveals that the parasitic capacitance material is the TiO2. The high partial pressure of TiCl4 leads to an increased oxygen-titanium ratio (O/Ti ratio) and a decreased maximum position of valance band at the interface between TiN and SiO2, which is attributed to TiO2 formation. Furthermore, we investigated the effect of the thickness of TiO2 and its Oxygen intensity induced by TiCl4 gas treatment on the change of the parasitic capacitance using X-ray fluorescence (XRF) analysis and Secondary Ion mass spectrometry (SIMS).