Study of TID Radiation Effects on the Breakdown Voltage of Buried P-Pillar SOI LDMOSFETs

Abstract

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on,sp</sub> ) of the SOI BP-LDMOS is 9.5 mΩ· cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si).