Abstract
The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.
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