STUDY OF THE MULTI-INPUT LUT COMPLEXITY

Abstract

Сontex. The programmable logic integrated circuits FPGA (field-programmable gate array) used realization of the generator offunctions LUT (Look Up Table), which is configured by loading a configuration memory for calculating a logic function in perfectdisjunctive normal form (PDNF). The LUT dimension determines the technological limitations of Mead and Conway on the number ofseries-connected MOS transistors. The standard number of LUT inputs for many years was 3 or 4, and 4-LUT is constructed from two 3-LUTs with an additional 1-LUT. However, in many projects, it is required to calculate functions of a large number of arguments. Thisrequires a multi-input LUT, which is built as a decomposition of 3-LUT, 4-LUT. The speed of computing logic functions determines by thedelay in the coupling matrices, so this decomposition leads to a decrease in performance. In recent years, the direction of adaptive logicalmodules (ALM) has been actively developing, in which the user has access to various versions of logical elements for five, six and evenseven, eight variables, which leads to an increase in performance. However, the manufacturer’s documentation does not provide a detaileddescription of the features of such multi-input LUTs, taking into account the Meade-Conway constraints. In addition, there are no estimatesof complexity and speed of multi-input LUTs. The analysis of sources allows suggests a further increase in the LUT bit capacity and theconvergence of FPGA and CPLD (complex programmable logic devices) capabilities in terms of bit depth. Therefore, studies of the featuresof constructing multi-input LUTs are relevant and the authors attempted to analyze the implementation of such prospective multi-bit logicObjective. The purpose of this work is to estimate the complexity and speed of the decomposition of a multi-bit LUT.Method. Obtaining expressions for estimating the complexity and speed of decomposition of a multi-bit LUT on a LUT of a lower bitlength.Results. A comparison of the complexity and delay in the number of transistors in the decomposition of a multi-bit LUT in thecomputer mathematics system Mathcad is performed.Conclusions. The conducted researches made it possible to establish the features of constructing multi-bit LUTs and to evaluatevarious variants of decomposition with further increase in the LUT dimension with the subsequent choice of the optimal ALM variant.