CAD for Delay Optimization of Symmetrical FPGA Architecture through Hybrid LUTs/PLAs

Abstract

Reconfigurable architecture using FPGA devices provide a method to utilize the available logic resources on the chip for various computations. The basic ability of reconfigurable computing is to perform computations in hardware to increase performance, while retaining the flexibility of application software. The purpose of this paper is to evaluation of computational delay of FPGA devices for reconfigurable computing system by mixing of Look up tables (LUTs) and Programmable logic arrays (PLAs) architecture. The two main types of programmable logic devices, field-programmable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology. They are both widely used and each contributing particular strengths in the area of reconfigurable system design. We identified Hybrid LUTs/PLAs architectures as Hybrid Reconfigurable Computing Architectures (HRCA). The basis of the HRCA is that some parts of digital circuits are well-suited for execution with LUTs, but other parts help more from the PLAs structures. For several classes of high performance applications, HRCA offers significant savings in total computational delay comparison with a symmetrical FPGA which contain only LUTs. It also offers some improvements in logical area and power consumption.Experimental results based on MCNC benchmark circuit were performed on implemented CAD and compare between HRCA and symmetrical FPGA. Initially results indicate that noteworthy computational delay of symmetrical FPGA is reduced by using HRCA.