Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

Abstract

We report a study of strained Si metal-oxide-semiconductor field-effect transistors (MOSFET’s) fabricated using a high thermal budget. The impact of Si channel strain on MOSFET performance, leakage current, and yield is investigated for Si1−xGex virtual substrates having Ge compositions varying from 0% to 30%. Increasing the Ge fraction in the SiGe virtual substrate increases the amount of tensile strain in the Si layer and consequently increases the electron mobility. High levels of strain, however, reduce the critical thickness of strained Si, above which Si becomes metastable and susceptible to relaxation during high-temperature device fabrication. Increasing the Ge composition in the virtual substrate up to 30% is shown to result in significant enhancements in MOSFET drain current and transconductance due to increased strain in the device channels. However, cross-wafer electrical yield data as a function of Ge composition are reported and show that increasing Ge compositions above 15% simultaneously reduces device yield. Off-state leakage current and gate oxide interface trap density are also shown to increase significantly when the Ge content in the virtual substrate is raised above 25%. Trade-offs between device performance and wafer yield are thus presented. The results identify the appropriate parameter window for virtual substrate Ge composition if acceptable MOSFET on-state performance, off-state performance, device yield, and reliability are to be achieved using a high thermal budget process. Detailed physical and electrical analyses have been carried out in order to understand the causes of the degraded performance for high Ge content virtual substrates. The reduction in yield with increasing Ge composition is shown to be related to a combination of strain relaxation and as-grown material quality. The strain state has been studied using Raman spectroscopy, Schimmel etching, and transmission electron microscopy, in conjunction with electrical measurements. The ability of techniques commonly used to assess strain relaxation is critically examined. The degraded electrical performance for strained Si/Si0.70Ge0.30 devices is shown to correlate well with the presence of surface threading dislocations resulting from strain relaxation. The relative effects of as-grown material quality and strain relaxation on device performance have also been investigated. The impact of device operating conditions on performance enhancements has further been analyzed and implications for the design of both n- and p-channel strained Si/SiGe MOSFET’s are discussed.