Abstract
Si nanocrystal memory cells have been integrated in Flash-like stand-alone devices of 16 Mb along with high and low voltage CMOS logic circuitry. Process integration drawbacks such as nanocrystal residuals in the circuitry region have been eliminated by optimizing etching processes. The program/erase threshold voltage distributions of the memory sectors are well separated and narrow. The voltage distribution width is related to NC sizes, and bigger NCs induce cell reliability problems. Some reliability issues for endurance are also related to the use of ONO dielectric which acts as charge trapping layer, mainly causing program/erase window shift and threshold voltage distribution broadening during endurance.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.