Study of machine to machine overlay error for sub-60-nm memory devices

Abstract

According to the 2007 international technology roadmap for semiconductors, the overlay budget of 60nm memory devices is 11.3nm. To meet such a tight requirement, each overlay error budget should be controlled carefully. It turns out that scanner contributions due to machine to machine overlay (MMO) error are nearly half of the total overlay error budget. In a conventional way, overlay errors are corrected by ten linear terms: offset x and y, wafer rotation x and y, wafer magnification x and y, shot rotation x and y, and shot magnification x and y. Especially for the shot correction, average correction values are applied commonly for all shots. MMO cannot be compensated by only linear correction to meet such a tight specification any longer. In this article, a grid matching strategy through per-shot-correction (PSC) is investigated so that scanner contributions are minimized. In PSC, shot correction is implemented for each shot with different correction parameter values. By matching wafer grids from machine to machine, overlay budget is feasible for sub-60-nm memory devices.