Advance overlay correction beyond 32nm DRAM process

Abstract

Overlay requirements for semiconductor devices are decreasing faster than anticipation. Beyond 50nm technology node, overlay budget becomes much tighter as 20% of half pitch. If Double Patterning Technology implemented, CD error will consume overlay control budget, which must be tighter than 1nm or 2nm. For 32nm technology node, the overlay control budget might be less than 5nm. In this paper, we studied the possibility of 5nm overlay control by using Zone Alignment (ZA), High Order Correction (HOC) and Correction Per Exposure (CPE). ZA is a novel zone dependency alignment strategy which compensates an improper averaging effect through weighting all surrounding marks with a linear model. HOC is an alignment correction method which can compensate nonlinear overlay error up to fifth order polynomial. CPE is a function of Grid-Mapper package, which is a field base method to correct overlay error field by field. It's also a good approach to minimize the grid fingerprint difference between exposure tools. The results of this paper indicate that ZA and HOC can reduce 15~25% uncorrectable overlay residual against conventional linear model and the stability in mass production has been demonstrated. Therefore, it is still not possible to control overlay within 5nm. CPE shows very good overlay residual performance as our expectation, and it's a possible approach to achieve 5nm overlay control in 32nm technology node. In addition, the feedback or feed-forward mechanisms have to be established for mass production worthy.