Abstract

An antimony (Sb)-doped substrate is used to fabricate high voltage power metal oxide semiconductor field effect transistor (MOSFET) to prevent out-doping phenomenon. Since the contact resistance of Sb-doped substrate is higher than that of the phosphorus (P) and arsenic (As)-doped substrates, which are widely used for low breakdown voltage power MOSFETs, devices that are fabricated with an Sb substrate have a higher source–drain forward voltage (VSD). The increased VSD is associated with power loss while the device is under switching in an inductive load bridge circuit. In this work, devices were baked at different temperatures for various times to reduce the VSD. The VSD was efficiently reduced at 300 °C after 6 h baking.

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