Study of amorphous silicon high voltage transistors using novel electron microscopy techniques

Abstract

Variants of scanning electron microscopy techniques developed by the authors allow detailed studies to be performed of the operation of thin-film active semiconductor devices. In particular, using a synchronised gating procedure, we are able to obtain time-resolved measurements of the spatial distribution of electrical charge throughout the operational cycle of the high voltage thin film transistors (HVTFTs) developed by Tuan and colleagues at Xerox's Palo Alto Research Centre. These devices operate in a space-charge limited mode. Consequently, the time evolution of charge within the channel, the residual trapped charge, etc. are of critical importance. Hack and co-workers at Xerox have generated computer simulations of such characteristics, but we believe that the present programme represents the first direct experimental investigation. In this paper, we outline the experimental technique and present some of the initial results of the study.