Abstract
In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key knob in designing the devices. It is experimentally observed that the hysteresis window of FE-FDSOI/FE-FinFET is decreased with (i) increasing the area of the ferroelectric capacitor and/or (ii) decreasing the gate area of baseline FET. The way how to control the hysteresis window of FE-FDSOI/FE-FinFET is proposed and discussed in detail.
Highlights
Digital computer has been faced with a few technical issues/limits, primarily because of ever-increasing power density [1, 2]
It turned out that the hysteresis window of FE-fully-depleted silicon-on-insulator (FDSOI) and FE-finshaped field-effect transistor (FinFET) can be controlled by modulating the top-electrode area of ferroelectric capacitors
The hysteresis window of FE-FDSOI and FE-FinFET was measured in terms of the resultant difference in the threshold voltages (Vth) during the forward and reverse sweeps, as follows: Hysteresis = Vth_FE−FDSOI/FinFET _forward
Summary
Digital computer has been faced with a few technical issues/limits, primarily because of ever-increasing power density [1, 2]. The impacts of (i) top-electrode area of ferroelectric capacitor and (ii) device dimensions of baseline FET on the hysteresis window are experimentally and systematically investigated.
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