Abstract
The RD53A is a prototype of the readout chip that will be used in the Compact Muon Solenoid (CMS) pixel detector after the High-Lumi LHC (HL-LHC) upgrade is complete beyond 2025. A new feature of the chip enables the writing of configuration commands between triggers during operation. This feature can be used to compensate for a detuning of the pixels due to radiation damage or temperature fluctuations over time. This paper studies the efficiency of such a method as well as its side-effects and the dependency on its parameters using an equivalent software implementation.
Highlights
Tracking using a pixel detector requires threshold uniformity over the pixel matrix for an accurate measurement of cluster hits, which in turn leads to a better track reconstruction [1]
The RD53A is a prototype of the readout chip that will be used in the Compact Muon Solenoid (CMS) pixel detector after the High-Lumi LHC (HL-LHC) upgrade is complete beyond 2025
The calibration will deteriorate over time due to single event upsets (SEU), increasing total ionizing dose (TID), and changes in temperature
Summary
Tracking using a pixel detector requires threshold uniformity over the pixel matrix for an accurate measurement of cluster hits, which in turn leads to a better track reconstruction [1]. An on-chip implementation of trickle tuning is described in [9] It consists of a drive clock regularly decreasing the threshold of the pixel matrix while every noise hit detected by a pixel will increase its threshold. An alternative way to implement trickle tuning is considered It relies on regular injections of a specific charge into a small subset of the pixel matrix and on updates of the TDAC values of the pixels according to their occupancy. The presented algorithm allows the testing of important aspects of trickle tuning using a more flexible software implementation instead of an implementation in the FPGA firmware It can show how well and how fast a calibrated threshold distribution can be reached. This method was implemented using the BDAQ53 framework [10] to calibrate the Linear Front End (LFE) of the RD53A chip during the process of data taking
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