Abstract
An application of multi-bit multipliers in universal computers and special processors for data encryption is analyzed. The use of single-bit half- and full adders with extremely minimal hardware and time complexity is substantiated. The structures of multi-bit streaming multipliers based on high-performance adder matrices with para-phase inputs and outputs are proposed. The characteristics of hardware and time complexity of this class of multipliers depending on the binary digits are investigated. The proposed structure and the system characteristics of multi-bit streaming multipliers with advanced functionality, which allow testing the correctness of the multiplication and cryptographic protection of the output information streaming of the multiplier by Galois codes are explored.
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