Design a pocket multi-bit multiplier in FPGA

Abstract

The multi-bit multiplier is an arithmetic unit which is often used in digital electronic systems and digital signal processors. There are two kinds of algorithm for performing multi-bit multiplication. According to the algorithm given in the paper, two kinds of simple multi-bit multiplier are introduced. Dealing with the structure of the combinational multiplier and sequential multiplier, the paper presents a discussion on the delay and resource utilization ration of an FPGA. The sequential multiplier has a more compact structure than the combinational multiplier. In the sequential multiplier, the carry circuit structure of the adder unit has an important influence on delay and resource utilization of the LCA. The connection mode of the adder unit given in the paper is acceptable and reasonable. The FPGA is an ideal device to implement a sequential multiplier. But if we want to design a more compact sequential multiplier in FPGA, then there are still many problems to overcome.