Structure mémoire reconfigurable. Vers une structure de stockage faible consommation

Abstract

It is now admitted that the memory in a system-on-chip will represent up to 90 % of the silicon area. Thus, the increase in the static power induced by the memory will become a major challenge for low-power system design. To overcome this problem, the reconfigurable architecture paradigm seems to be a challenging issue. This paper presents a new architecture suitable for the memory hierarchy that introduces reconfigurable properties and supply voltage dynamic management. Theoretical results show that significant energy savings can be achieved.