Stress-Voiding and Electromigration in Multilevel Interconnect Metallizations

Abstract

ABSTRACTStress-voiding or stress migration (SM), and electromigration (EM) are urgent problems in ULSI microcircuits with features in the submicron range. Severe stress-voiding arises in multilevel metallizations because of the high constraint offered by the refractory metal layers, the ceramic insulation, and the rigid contact and via structures which prevent plastic relaxation of the thermally induced stresses. Also, W-plugs and/or refractory barrier layers block entirely the EM flux, resulting in an enhanced probability of EM damage. We review the physical bases of a recently introduced unified SM and EM model [1,2]. We apply the model to an interconnect line confined by vias at both ends and derive equations which explicitly show the effects of external conditions and microstructural parameters on the evolution of SM and EM damage. Particularly we analyze the effects of Cu depletion on void growth rate at vias. We also show how the shifts in the line resistance are related to void growth. Finally we demonstrate that the model predictions compare well with the recently published experimental EM data.