Stress and electromigration modelling for confined chip level interconnect lines

Abstract

Stress evolution due to electromigration at blocking boundaries in the chip level interconnect lines has been recognized as an important failure mechanism, leading eventually to void formation or hillocking. The Cornell unified stress migration (SM) and electromigration (EM) model was introduced in the 1st Stress Workshop [1], held in Ithaca 1991. In this ‘atomic EM model’ the electric current and the stress gradient act as atomic driving forces resulting in SM and EM damage. In the case of substitutional vacancy diffusion, the atomic EM model can also be expressed in terms of vacancy concentration, resulting in a ‘vacancy EM model’. In the case of vacancy diffusion, when the atomic diffusivity is directly related to the stress, both atomic and vacancy EM equations must be solved numerically. However, simple approximate analytic solutions exist for the cases when the atomic diffusivity can be taken constant. We show that the approximate analytic solutions to the atomic EM equation agree more closely with the exact ones than the corresponding solutions to the vacancy EM equation. The difference can be traced back to the fact that the form of atomic EM equation remains valid whether the diffusivity is constant or not, which is not the case for the vacancy EM equation. Finally, we show that model the atomic EM model leads to predictions that are amenable to experimental verification.