Stresses in 3D SiP with TSV under steady thermal loads

Abstract

In the late 1990s, the technology that is stacked multiple silicon chips on the package was developed [1]. Then SiP (System in Package) constructed with CPU and memory into a package is appeared. Recently, downsizing and high-performing of semiconductor packages have been studied. In conventional SiP, several semiconductor chips had been arranged in a plate [2-6]. Therefore, it is difficult to correspond to downsizing and high-performing of electronic devices because that large area was occupied by the package. In order to solve above problems, semiconductor chips have been stacked and TSV (Through Silicon Via) have been used to communicate between the mutual chips. The 3D-stacked structure for ultra high speed camera developed by ASET (Association of Super-Advanced Electronics Technologies)[7, 8] is shown in Fig.1. TSV (copper) is electrode through silicon chip and micro bump (copper)[9] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress depend on temperature increment. In case of 3D-SiP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp by difference of expansion of material. Therefore simulations with detail model must be desired for accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in package were modeled due to large number of numerical data even if the latest computing systems have been adopted. In this study, stresses of Si and TSV in 3D SiP were discussed with the model which was partially replaced by simplified semiconductor chip. It was shown that inner part of package was replaced on simplified model and outer part is the model constructed by Si chip, TSVs and micro bumps.