Stress simulation and design optimal study for Cu pillar bump structure

Abstract

In recent years, Cu pillar bump technology was proposed intensely in place of solder bump to achieve more I/Os signals, better electrical characteristics and cheaper price requirements by enlarging substrate circuit layout density, reducing substrate layers and narrowing package sizes. Cu pillar bump may suffer potential Extreme low-k (ELK) crack or delamination due to Cu post has higher modulus compared to solder bump to induce higher ELK stress, especially in thinner ELK wafer technology. Therefore, in the beginning of the paper, four kind of bump structures were investigated as PI pull in - PI pull out - FOC and exposed pad bump structure in Cu pillar bump structure technology to discover the strong and weak points in ELK stress by Finite Element Method (FEM). Besides the Cu pillar bump structure selection, this study also aims to discuss geometry combinations of UBM size, UBM geometric shape, passivation opening, Al pad size, Al pad thickness, PI opening, PI thickness, bump height, die thickness to propose the optimal design with lower ELK delamination risk. Furthermore, the core material and underfill material were also considered with different candidates to compare the ELK stress level. In order to make the novel package with Cu pillar bump structure pass the reliability test, lots of simulations were done to reduce ELK stress. According to the simulation results, optimal design was approached to effectively reduce ELK stress as PI pull in bump structure, larger UBM size, oval UBM shape, more solder tip volume, thinner die thickness and suitable material of low CTE core material combined with stacked-up substrate and higher Tg underfill to pass reliability test to achieve successfully development of Cu pillar bump structure.