Copper pillar bump structure optimization for flip chip packaging with Cu/Low-K stack

Abstract

Copper pillar bumping is a promising solution to cope with the challenges which flip chip packages face when bump pitch size keep shrinking. A large FCBGA(flip chip ball grid array) package for 45nm Cu/Low-K device with Cu pillar bumps is chosen to investigate the package reliability. Finite element models have been built with multi-level sub-modeling technique to consider the detailed Cu/Low-K structure in the chip. Comparison on Cu pillar bumps vs. solder bumps shows the former bump type generated about 20∼30% higher stress on Cu/lowK structure. Thus package reliability may become a concern when Cu pillar is used. To improve the package reliability, design optimization is carried out on Cu pillar bump structure. DOE (design of experiment) study is done on the following factors: Cu pillar height, PI (polyimide) passivation opening and PI thickness etc. Loading is considered for both post flip chip attach process (reflow) and after full assembly (curing). It is found that the stress in post flip chip attach process is much higher than that after full assembly. For Cu/low-K devices, special care is needed for flip chip attach process. Stress on Cu/low-K interface has been analyzed in detail, and it is shown that the interface stress pattern is highly dependent on UBM structure design, especially PI opening and thickness. An overall picture of the PI effect is presented based on optimization results. Lower Cu pillar height, smaller PI opening and higher thickness are recommended for bump structure design.