Stress-induced trench narrowing in Cu interconnect of sub-20 nm node: FEM simulation

Abstract

The trench narrowing at sub-20nm BEOL process has been reproduced using a FEM simulation. The trench narrowing can be observed under the conditions of both the high intrinsic stress of a hard mask and the specific design of metal line patterns with the length difference between center and side trenches. As the center trench length increases, a trench displacement takes place because trench walls have a high compressive stress gradient from the side trench surface to the center one in the direction parallel to the trench lines. The displacement also decreases with decreasing the width of the trench while increasing with decreasing the width of the low-k wall. The high pattern density of metal or dummy lines around the trenches decreases the displacement of the low-k dielectric walls. Considering the distribution of pattern densities at left and right sides of the trenches, a symmetrical pattern density deforms the trench wall more largely than an asymmetrical one. Young's modulus of SiOCH is not a sensitive factor on the trench narrowing. Our displacement analysis may be used in predicting hot spots of void defects in the Cu interconnect of real Si wafers.