Abstract
The poor interface quality of the Silicon Carbide/oxide (SiC/SiO2) interface severely degrades the electron surface channel mobility in SiC-based power devices. Based on transfer characteristic simulations (with a deck calibrated to experimental data), this work predicts improved mobility with stress engineering, a well-established technique for performance enhancement in low power silicon (Si) transistor technology. Process simulation of Si and SiC-based devices with Silicon Nitride (Si3N4) stressor layer has been carried out to estimate the stress generated in the channel. SiC D-MOSFET we have also computed the effect of varying stress magnitude, direction, and position in the device.
Highlights
Power transistors are designed to be operated in high voltage, high temperature environment
It is desirable to operate these power devices at high frequencies since that reduces the size of the passive elements, and thereby the overall size of the chip, allowing us to add on increased functionality
A plasma-enhanced chemical vapour deposition (CVD) process would be used for depositing such a stressor layer in Si MOS technology [41]–[43]
Summary
Power transistors are designed to be operated in high voltage, high temperature environment. Structure from process simulation, showing Si3N4 stressor, and the cut-line for stress profile. There is experimental literature showing improved mobility with externally applied strain in SiC planar MOSFETs [26], [27].
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