Strategy for Designing Single Electron Transistors

Abstract

Silicon-processing, ultra-low-power dissipation, and scalability attract SET as the most emerging nanodevice. The SET, working on the principles of Coulomb blockade (CB) and Quantum mechanical tunneling (QMT), has many challenges at the design level. Its structure consists of two ultra-thin tunnel barriers and a conductive island which is always challenging to design. In this work, tunnel barrier optimization and island engineering are targeted to design SET with high current density and with appropriate CB. The Aluminum and N-type phosphorus-doped polysilicon materials are used as the island materials. The tunnel barrier thickness has been varied from 1 nm, 1.5 nm, 2 nm, 3 nm, and 4 nm. The simulations are carried out to plot I-V and Q-V plots in Sentaurus TCAD. The behavior of CB and QMT has been analyzed at 77 K, 150 K, 300 K, and 400 K. From the simulations of all structures the maximum drain current is found in range the 1 nA (TJ = 4 mm and at 77 K) to 3.5 μA (TJ = 1 mm and at 400 K) for Aluminum island and 2e-4 pA (TJ = 2 mm and at 77 K) to 0.35 nA (TJ = 1 mm and at 400 K) for Polysilicon island. Mathematical analysis for CB has been done for the above-mentioned temperatures and compared with simulations. The Effect of the gate on the controlling of QMT is analyzed on the 3 nm tunnel junction thick Aluminum island SET. The results of the maximum drain current have been compared to the other research works.