Island Engineering of Single-Electron Transistor for Room Temperature Operation

Abstract

Single-electron transistors (SETs) have shown their competence to overpower MOSFETs as well as FinFETs in low power regime. However, research to exhibit room temperature operation and its demonstration for application in logic and memory circuits is still in infancy. A SET contains two ultra-thin tunnel barriers and a conductive island which work on the principle of Coulomb blockade (CB) and tunneling. Its dimensions must be planned properly to exhibit room temperature operation with CMOS compatibility. In this work, the island engineering technique is proposed for devising SET so as to observe both Coulomb blockade and quantum mechanical tunneling at room temperature. The island engineering is carried out for aluminum and copper island. The SET has been simulated in TCAD using the designed dimensions and its output as well as transfer characteristics have been plotted at room temperature. The analyses illustrate that out of all the SET devices, aluminum island SET with 4 nm tunnel barrier with 17 nm island length offers the desired CB and tunneling current in tens of nA range. To validate the results and ascertain the concept of CMOS compatible design, SET transfer and output characteristics have been simulated using Cadence Virtuoso using MIB model. The proposed technique of SET is also compared with the other SET optimization techniques.