Strategies for nanoelectronics

Abstract

Denoting with ‘nanodevice’ any device with size in one dimension at least in the nanometre length scale (NLS), the basic constituent of integrated circuits (ICs), the metal-oxide-semiconductor (MOS) field-effect transistor (FET), is by several years a nanodevice. In fact, the thickness of the SiO 2 gate dielectric is around 3 nm for logics or 5 nm for nonvolatile memories. However, since the factors limiting the IC integration are horizontal sizes, in electronics one speaks of nanodevice when its size in one horizontal dimension at least is in the NLS. The definition of features in the NLS is impossible via optical lithography, but can be done using electron- or ion-beam lithography. These techniques, however, are very expensive and still in their fancy, at least for what concerns their exploitation in the industry practice. Geometries in the NLS can however be produced with relative ease by the spacer patterning technique, i.e., transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length producible in this way is controlled by: the steepness of the step defining the sacrificial layer; the uniformity of the deposited or grown films; and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology, where each layer useful for defining the FET should be in the NLS and aligned on the underlying geometries with tolerances in the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents of nanoICs (molecules, supramolecular structures, clusters, etc.), any nanoIC can hardly be prepared without the ability to produce arrays of conductive strips with pitch in the NLS. This work is devoted to describe a scheme (essentially based on the existing microelectronic technology) for their production without the use of electron- or ion-beam lithography and used as host of molecular devices.