A hybrid approach to nanoelectronics

Abstract

The definition of features on the nanometre length scale (NLS) is impossible viaconventional lithography, but can be done using extreme ultraviolet, synchrotron-radiation,or electron beam lithography. However, since these techniques are very expensive and stillin their infancy, their exploitation in integrated circuit (IC) processing is still highlyputative. Geometries on the NLS can however be produced with relative ease using thespacer patterning technique, i.e. transforming vertical features (like film thickness) inthe vicinity of a step of a sacrificial layer into horizontal features. The ultimatelength that can be produced in this way is controlled by the steepness of the stepdefining the sacrificial layer, the uniformity of the deposited or grown films, andthe anisotropy of its etching. While useful for the preparation of a few deviceswith special needs, the above trick does not allow by itself the development of ananotechnology where each layer useful for defining the circuit should be on the NLS andaligned on the underlying geometries with tolerances on the NLS. Setting up such ananotechnology is a major problem which will involve the IC industry in the post-Roadmapera. Irrespective of the detailed structure of the basic constituents (molecules,supramolecular structures, clusters, etc), ICs with nanoscopic active elements can hardly beprepared without the ability to produce arrays of conductive strips with pitchon the NLS. This work is devoted to describing a scheme (essentially based onthe existing microelectronic technology) for their production without the useof advanced lithography and how it can be arranged to host molecular devices.