Strategies for improving the reliability of solder joints on power semiconductor devices

Abstract

In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi‐chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple‐stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite‐element analyses of an interconnection structure, termed the Dimple‐Array Interconnect, for improving the solder joint reliability is also presented.