Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

Abstract

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.