Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Abstract

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies.