Stochastic Number Generators with Minimum Probability Conversion Circuits

Abstract

A stochastic number generator (SNG) is used to convert binary radix encoded numbers to bit-streams in stochastic computing. An SNG consists of two components: a random number source (RNS) and a probability conversion circuit (PCC). While both the hardware area overhead and hardware cost for arithmetic operations are significantly less in stochastic computing than in binary computing, the area overhead and cost for an SNG is substantial. In this paper, we propose two minimum PCC (MPCC) designs, with minimum logic in terms of 2-input gates, that reduce the hardware cost of an SNG. The proposed MPCCs generate bit-streams with very low correlation when used with two SNGs that share one RNS. Compared to prior work, the proposed MPCCs can reduce the hardware cost for a 12-bit SNG up to 67%.