Design and Implementation of Efficient Stochastic Number Generator

Abstract

Stochastic Computing (SC) is a logical computational technique that performs operations on random bit streams. These random bit streams are generated using stochastic number generators (SNG). In the circuits using stochastic computing, SNGs consume most of the physical area and power. This paper proposes power and speed efficient 4-bit and 8-bit SNGs by using modified Non-linear Feedback Shift Register (NLFSR) as Random Number Source (RNS) and by applying the concept of sharing of an RNS with many SNGs. An n bit NLFSR can generate all 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> random sequences. The 4-bit and 8-bit NLFSRs, designed using the bipartite technique, are proposed to reduce the delay and power consumed by the SNG. In this paper, proposed 4-bit and 8-bit SNGs are designed and implemented using Xilinx ISE tool and their performance concerning area, power, and delay, are evaluated with Cadence Genus synthesis solution in 45nm technology. The performance of proposed SNGs is compared with the existing SNGs and this comparison shows that the proposed SNGs are more efficient in terms of power and speed. It is also observed that as the number of bits increases, the reduction in power consumption and delay also increases for the proposed design with respect to the existing design.