Stochastic model based dynamic power estimation of microprocessor using Imperas simulator

Abstract

This paper presents a novel approach for instruction-level power profiling of microprocessor using a simulator — Imperas. A stochastic model has been developed to profile power dissipation due to micro operations performed by the microprocessor. The microprocessor with all peripherals was completely configured in the Imperas Open Virtual Platform. The methodology involves designing Imperas VAP Tools based Binary Interception Library to capture various micro activities for an application being executed. An open source Open RISC 1000 core has been employed as a target processor. A characteristic profile and stochastic data that include instruction type, number of instructions, simulation time, statistics of cache and bus activities, etc. are extracted for the application on virtual platform. Various dynamic losses associated with the processor have been incorporated using stochastic models. Prominent advantage of our proposed power profiling technique is that the accuracy and preciseness are proportional to the number of instructions executed in the application. Complete architecture of Open RISC 1000 has been profiled in terms of power dissipation by micro operations performed due to execution of a group of instructions. Moreover, algorithms with different time-complexities have also been compared for their power efficiency and the effect of increasing the number of cores of microprocessor on power dissipation in a multi-core system has also been explored. This technique results in very fast power estimation as conventional RTL level simultaneous testing of software and hardware is complex.