Stochastic collocation method for interconnect delay estimation in the presence of process variations

Abstract

We present a process variations based stochastic collocation method to estimate interconnect delay. This method translates the strongly correlated process variations into orthogonal random variables by Cholesky decomposition. Polynomial chaos expression （PCE） and stochastic collocation method （SCM） are used to analyse the system response. A finite representation of interconnect delay is then obtained by using the collocation approach of minimizing the Hilbert space norm of the residual error. Experiment demonstrates that results obtained from the analysis method agree well with that from HSPICE simulation. The difference between the delays obtained from the analytical method and that from HSPICE is about 0.2% or less. Moreover, the method shows good computational efficiency, and much less running time has been observed compared with HSPICE simulation.