STI process steps for sub-quarter micron CMOS

Abstract

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μm CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.